Side-channel attacks are a significant threat to cryptography hardware. Analysis models can be observed and exploited for an attacker to extract the “secret key of cryptographic hardware”. EM side-channel leakage analysis (SCLA) techniques for cryptographic integrated circuit chips are a “near-noninvasive alternative” where attackers can derive even more information from a “silicone integrated circuit” (IC) chip using magnetic probes. While previous works have attempted countermeasures against side-channel attacks, the techniques are tested “through post-silicon evaluation” which poses problems in the cost and physical accuracy of the SC leakage. The pre-silicon SCLA simulation approach mitigates many of these problems, but the technique needs to simulate the behaviors of power and EM side-channel leakages while maintaining its “efficiency, accuracy, and capacity to handle the full-chip and system level design database”. This article proposes such a pre-silicon SCLA method where fast “simulation-based power” and EM SCLA techniques are applied to cryptographic hardware. EM SCLA evaluates the magnetic fields within the power supply current. A “power noise solver” and “EM solver” are proposed in the flow to simulate “traces during cryptography module simulation”. Utilizing a “security-sensitive register extraction engine”, “intelligent probe generation flow”, and direct vector control, the flow is optimized in speed. The article demonstrates that their method of EM SCLA is effective in evaluating SC leakage by comparing their results to experimental measurements of a 0.13 μm test chip.
